1 of 13
REV: 040805
FEATURES
Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit and
Lithium Energy Source
Clock Registers are Accessed Identically to
the Static RAM. These Registers are
Resident in the Eight Top RAM Locations.
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
BCD-Coded Year, Month, Date, Day, Hours,
Minutes, and Seconds with Leap Year
Compensation Valid Up to 2100
Power-Fail Write Protection Allows for
10% V
CC
Power Supply Tolerance
DS1644 Only (DIP Module)
Upward Compatible with the DS1643
Timekeeping RAM to Achieve Higher
RAM Density
Standard JEDEC Bytewide 32k x 8 Static
RAM Pinout
DS1644P Only (PowerCap
Module Board)
Surface Mountable Package for Direct
Connection to PowerCap Containing
Battery and crystal
Replaceable Battery (PowerCap)
Power-Fail Output
Pin-for-Pin Compatible with Other Densities
of DS164XP Timekeeping RAM
Underwriters Laboratory (UL) Recognized
PIN CONFIGURATIONS
ORDERING INFORMATION
PART
VOLTAGE
RANGE (V)
TEMP RANGE PIN-PACKAGE
TOP MARK
DS16440120+
5.0
0C to +70C 32 EDIP (0.740a)
DS1644+120
DS16440-120
5.0
0C to +70C 32 EDIP (0.740a)
DS1644-120
DS1644P120+
5.0
0C to +70C 34 PowerCap*
DS1644P+120
DS1644P-120
5.0
0C to +70C 34 PowerCap*
DS1644P-120
*DS9034-PCX, DS9034I-PCX, DS9034-PCX+ required (must be ordered separately).
A "+" indicates a lead-free product. The top mark will include a "+" symbol on lead-free devices.
1
NC
2
3
NC
NC
PFO
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
A14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
NC
X1 GND V
BAT
X2
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
15
13
27
28-Pin Encapsulated Package
(720-mil Extended)
A7
A5
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
1
2
3
4
5
6
7
8
9
10
11
12
14
28
26
25
24
23
22
21
20
19
18
17
16
A12
A6
A4
A14
DS1644/DS1644P
Nonvolatile Timekeeping RAM
www.maxim-ic.com
PowerCap is a registered trademark of Dallas Semiconductor.
DS1644/DS1644P
2 of 13
PIN DESCRIPTION
PIN
PDIP PowerCap
NAME FUNCTION
1 32 A14
2 30 A12
3 25 A7
4 24 A6
5 23 A5
6 22 A4
7 21 A3
8 20 A2
9 19 A1
10 18 A0
Address Input
11 16 DQ0
12 15 DQ1
13 14 DQ2
Data Input/Output
14 17 GND
Ground
15 13 DQ3
16 12 DQ4
17 11 DQ5
18 10 DQ6
19 9 DQ7
Data Input/Output
20
8
CE
Active Low Chip-Enable Input
21 28 A10
Address
Input
22
7
OE
Active Low Output-Enable Input
23 29 A11
24 27 A9
25 26 A8
26 31 A13
Address Input
27 6 WE
Active-Low Write-Enable Input
28 5 V
CC
Power-Supply
Input
- 4
RST
Active-Low Reset Output, Open Drain. Requires a pullup resistor for
proper operation.
- 1-3,33,34 NC No
Connection
- X1,
X2,
V
BAT
Crystal Connection V
BAT
Battery Connection
DESCRIPTION
The DS1644 is a 32k x 8 nonvolatile static RAM with a full function real time clock, which are both
accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any
JEDEC standard 32k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and
EEPROM, providing read/write nonvolatility and the addition of the real time clock function. The real
time clock information resides in the eight uppermost RAM locations. The RTC registers contain year,
month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the
month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access
of incorrect data that can occur during clock update cycles. The double-buffered system also prevents
time loss as the timekeeping countdown continues unabated by access to time register data. The DS1644
also contains its own power-fail circuitry, which deselects the device when the V
CC
supply is in an out-of-
tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by
low V
CC
as errant access and update cycles are avoided.
DS1644/DS1644P
3 of 13
PACKAGES
The DS1644 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1644P after the completion of the surface-mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS--READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1644 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was present at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1644 registers are updated simultaneously after the clock
status is reset. Updating is within a second after the read bit is written to 0.
DS1644 BLOCK DIAGRAM Figure 1
DS1644 TRUTH TABLE Table 1
V
CC
CE
OE
WE
MODE DQ POWER
V
IH
X X DESELECT
HIGH-Z STANDBY
X X X DESELECT
HIGH-Z STANDBY
V
IL
X V
IL
WRITE
DATA
IN ACTIVE
V
IL
V
IL
V
IH
READ
DATA
OUT
ACTIVE
5V
10%
V
IL
V
IH
V
IH
READ
HIGH-Z ACTIVE
<4.5V >V
BAT
X
X
X
DESELECT
HIGH-Z
CMOS
STANDBY
<V
BAT
X
X
X
DESELECT
HIGH-Z
DATA
RETENTION
MODE
DS1644/DS1644P
4 of 13
SETTING THE CLOCK
The MSB Bit, (B7) of the control register is the write bit. Setting the write bit to a 1, like the read bit,
halts updates to the DS1644 registers. The user can then load them with the correct day, date and time
data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The
OSC
bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid
(i.e.,
CE
low,
OE
low, and address for seconds register remain valid and stable).
CLOCK ACCURACY (DIP MODULE)
The DS1644 is guaranteed to keep time accuracy to within
1 minute per month at 25C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. Clock accuracy is also affected by the electrical environment and caution should be taken to
place the RTC in the lowest level EMI section of the PCB layout. For additional information please see
application note 58.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1644 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within
1.53 minutes per month (35 ppm) at 25C. Clock
accuracy is also affected by the electrical environment and caution should be taken to place the RTC in
the lowest level EMI section of the PCB layout. For additional information please see application note
58.
DS1644/DS1644P
5 of 13
DS1644 REGISTER MAP--BANK1 Table 2
DATA
ADDRESS
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
FUNCTION
7FFF -- -- -- -- -- -- -- -- Year 00-99
7FFE X X X -- -- -- -- -- Month 01-12
7FFD X X - -- -- -- -- -- Date 01-31
7FFC X
FT
X
X
X
--
--
-- Day 01-07
7FFB X X -- -- -- -- -- -- Hour 00-23
7FFA X -- -- -- -- -- -- -- Minutes 00-59
7FF9
OSC
-- -- -- -- -- -- -- Seconds 00-59
7FF8 W R X X X X X X Control A
OSC = STOP BIT
R = READ BIT
FT = FREQUENCY TEST
W = WRITE BIT
X = UNUSED
Note: All indicated "X" bits are unused but must be set to "0" during write cycles to ensure proper clock
operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1644 is in the read mode whenever
WE
(write enable) is high, and
CE
(chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t
AA
after the last address input is stable, providing that the
CE
and
OE
access times and states are satisfied. If
CE
or
OE
access times are not met, valid data will be
available at the latter of chip enable access (t
CEA
) or at output enable access time (t
OEA
). The state of the
data input/output pins (DQ) is controlled by
CE
and
OE
. If the outputs are activated before t
AA
, the data
lines are driven to an intermediate state until t
AA
. If the address inputs are changed while
CE
and
OE
remain valid, output data will remain valid for output data hold time (t
OH
) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1644 is in the write mode whenever
WE
and
CE
are in their active state. The start of a write is
referenced to the latter occurring high to low transition of
WE
or
CE
. The addresses must be held valid
throughout the cycle.
CE
or
WE
must return inactive for a minimum of t
WR
prior to the initiation of
another read or write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a typical application, the
OE
signal will be high during a write cycle. However,
OE
can be
active provided that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on
WE
will then disable the outputs t
WEZ
after
WE
goes active.
PDF 
ZIP